This relates generally to imaging systems and, more particularly, to imaging systems that are provided with column memory test and repair circuitry.
Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an electronic device is provided with an array of image pixels arranged in pixel rows and pixel columns. Circuitry is commonly coupled to each pixel column for reading out image signals from the image pixels.
In a conventional arrangement, the pixel columns are connected to column memory circuitry. The column memory receives pixel signals from selected image pixels in the image pixel array and stores the received pixel signals. The column memory is sometimes used to implement correlated double sampling (CDS) and desired signal binning by combining the values of adjacent image pixels.
It is generally desirable to test the functionality of the column memory and to repair the column memory when a defect is detected. A typical column memory testing procedure involves performing row-wise column memory test and repair. Consider a scenario in which an image sensor under test includes 28 rows, where the first 23 bits in each column is normally in use, and where the remaining five bits are redundant bits used for repair. A first test is performed without repair to check if the first 23 rows exhibit any defects. If there is no defect, the sensor does not require any repair. If a defect is detected, a second test is performed on the five remaining redundant rows to help repair the defect. Passing redundant rows can then be used to substitute defective rows in the first 23 rows.
Performing row-wise column memory repair in this way may be time-consuming and costly. It would therefore be desirable to provide imaging systems with improved column memory repair capabilities.